*** Somy Timer Example ***
http://www.xiajiashan.com
#include "lpc1114.h"
#include "typedef.h"
#define LED1 (1 << 9) //PIO1_9
#define LED2 (1 << 10) //PIO1_10
#define KEY1 (1 << 0) //PIO1_0
#define KEY2 (1 << 1) //PIO1_1
#define TMR16B0_CLK (1<<7)
void led_on(uint32 num)
{
GPIO1DATA_ALL &= ~num; // 亮
}
void gpio_dir_set(uint32 num)
{
GPIO1DIR |= num;
}
void led_off(uint32 num)
{
GPIO1DATA_ALL |= num; // 灭
}
void time0_init(void)
{
TMR16B0PR = 99; // 设置定时器分频为分频，得Hz
TMR16B0MCR = 0x03; // 匹配通道匹配中断并复位TMR16B0TC
TMR16B0MR0 = 110592; // 比较值(1S 定时值)
TMR16B0TCR = 0x03; // 启动并复位TMR16B0TCR
TMR16B0TCR = 0x01;
}
sys_AHB_clk_ctrl(uint32 xxx_ckl)
{
AHBCLKCTRL |= xxx_ckl;
}
int main(void)
{
sys_AHB_clk_ctrl( TMR16B0_CLK );
//把P1.9 和P1.10 引脚设置为输出
gpio_dir_set( LED1 | LED2 );
time0_init();
//关LED1 LED2
led_off( LED1 | LED2 );
while(1)
{
while((TMR16B0IR & 0x01)==0)
{
};
TMR16B0IR = 0x01;
if ( (GPIO1DATA_ALL & LED1) ==0 ) //如果LED1 亮
{
led_off( LED1 | LED2 );
}
else
{
led_on( LED1 | LED2 );
}
}
}
*** Somy timer defines ***
#define TMR16B0IR (*((volatile unsigned long *) 0x4000C000))
#define TMR16B0TCR (*((volatile unsigned long *) 0x4000C004))
#define TMR16B0TC (*((volatile unsigned long *) 0x4000C008))
#define TMR16B0PR (*((volatile unsigned long *) 0x4000C00c))
#define TMR16B0PC (*((volatile unsigned long *) 0x4000C010))
#define TMR16B0MCR (*((volatile unsigned long *) 0x4000C014))
#define TMR16B0MR0 (*((volatile unsigned long *) 0x4000C018))
#define TMR16B0MR1 (*((volatile unsigned long *) 0x4000C01c))
#define TMR16B0MR2 (*((volatile unsigned long *) 0x4000C020))
#define TMR16B0MR3 (*((volatile unsigned long *) 0x4000C024))
#define TMR16B0CCR (*((volatile unsigned long *) 0x4000C028))
#define TMR16B0CR0 (*((volatile unsigned long *) 0x4000C02c))
#define TMR16B0EMR (*((volatile unsigned long *) 0x4000C03c))
#define TMR16B0CTCR (*((volatile unsigned long *) 0x4000C070))
#define TMR16B0PWMC (*((volatile unsigned long *) 0x4000C074))
#define AHBCLKCTRL (*((volatile unsigned long *) 0x40048080))
*** Vilaca timer example ***
http://vilaca.eu/lpc1114/vilaca.eu.lpc1114_102_led_blink.zip
int main(void)
{
LPC_SYSCON ->SYSAHBCLKCTRL |= (1 << 8); // Enable Clock for TMR1
LPC_IOCON ->PIO1_9 |= (1 << 0); // PIN1_9 = CT16B1_MAT0
LPC_TMR16B1 ->MR0 = 2000; // 50% Duty Cycle
LPC_TMR16B1 ->PR = 12000;
LPC_TMR16B1 ->MR3 = 4000; // Cycle Length
LPC_TMR16B1 ->MCR |= (1 << 10); // TC Reset on MR3 Match
LPC_TMR16B1 ->PWMC |= (1 << 0); // PWM Mode
LPC_TMR16B1 ->TCR |= (1 << 0); // GO
while (1);
// unreachable
return 0;
*** lpc11xx.h ***
NXP LPC11xx CMSIS Cortex-M0 Core Peripheral Access Layer Header File V1.10 24nov 2010
*** Memory map ***
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_AHB_BASE (0x50000000UL)
/* APB0 peripherals */
#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
#define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000)
#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
/* AHB peripherals */
#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
*** Peripheral declaration ***
#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
#define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE )
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
*** GPIO typedef ***
typedef struct
{
union {
__IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 (R/W) Port data Register for pins PIOn_0 to PIOn_11 */
struct {
uint32_t RESERVED0[4095];
__IO uint32_t DATA; /*!< Offset: 0x3FFC (R/W) Port data Register */
};
};
uint32_t RESERVED1[4096];
__IO uint32_t DIR; /*!< Offset: 0x8000 (R/W) Data direction Register */
__IO uint32_t IS; /*!< Offset: 0x8004 (R/W) Interrupt sense Register */
__IO uint32_t IBE; /*!< Offset: 0x8008 (R/W) Interrupt both edges Register */
__IO uint32_t IEV; /*!< Offset: 0x800C (R/W) Interrupt event Register */
__IO uint32_t IE; /*!< Offset: 0x8010 (R/W) Interrupt mask Register */
__I uint32_t RIS; /*!< Offset: 0x8014 (R/ ) Raw interrupt status Register */
__I uint32_t MIS; /*!< Offset: 0x8018 (R/ ) Masked interrupt status Register */
__O uint32_t IC; /*!< Offset: 0x801C ( /W) Interrupt clear Register */
} LPC_GPIO_TypeDef;
*** Timer typedef ***
typedef struct
{
__IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */
__IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register */
__IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */
__IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */
__IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */
__IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */
__IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */
__IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */
__IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */
__IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */
__IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */
__I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */
uint32_t RESERVED1[3];
__IO uint32_t EMR; /*!< Offset: 0x03C (R/W) External Match Register */
uint32_t RESERVED2[12];
__IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */
__IO uint32_t PWMC; /*!< Offset: 0x074 (R/W) PWM Control Register */
} LPC_TMR_TypeDef;
*** LPC_SYSCON_TypeDef ***
...
typedef struct
{
...
__IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 (R/W) System AHB clock divider Register */
uint32_t RESERVED4[1];
__IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 (R/W) System AHB clock control Register */
uint32_t RESERVED5[4];
...
} LPC_SYSCON_TypeDef;
.END
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