Design notes
1. Selecting PIO0_8 pin for PWM
The pin to use is Pin 27, PIO0_8/MISO0/CT16B0_MAT0.
2. Setting PIO0_8 for 16 bit timer match register output (CT16B0_MAT0)
LPC11xx.h v1.1 2012nov24 uses the following struct for IO control/data registers.
typedef struct
{
...
__IO uint32_t PIO0_8; /*!< Offset: 0x060 (R/W) I/O con for pin PIO0_8/MISO0/CT16B0_MAT0 */
...
} LPC_IOCON_TypeDef;
LPC111x/LPC11Cxx User manual UM10398 Rev12 2012sep24 Table 79 says that bits 2:0 of the IOCON_PIO0_8 register selects the pin function.
IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060)
2:0 FUNC Selects pin function. All other values are reserved. 000
0x0 Selects function PIO0_8.
0x1 Selects function MISO0.
0x2 Selects function CT16B0_MAT0.
I will use PIO0_8 as CT16B0_MAT_0. So I will use the following 2 statements to set IOCON_PIO0_8 bits 2:0 to 0x2.
LPC_IOCON->PIO0_8 &= ~0x3; // set bits 2:0 to 0b00 (0x0);
LPC_IOCON->PIO0_8 |= ~0x2; // set bits 2:0 to 0b10 (0x2);
3. Enabling clock for 16 bit Timer/Counter 0.
LPC11xx.h uses the following struct for clock control.
typedef struct
{
...
__IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 (R/W) Main clock source select Register */
__IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 (R/W) Main clock source update enable */
__IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 (R/W) System AHB clock divider Register */
...
__IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 (R/W) System AHB clock control Register */
...
} LPC_SYSCON_TypeDef;
UM10398 Table 21. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080)
...
bit 6 GPIO Enables clock for GPIO. reset value = 1
0 Disable
1 Enable
bit 7 CT16B0 Enables clock for 16-bit counter/timer 0. reset value = 0
0 Disable
1 Enable
bit 8 CT16B1 Enables clock for 16-bit counter/timer 1. reset value = 0
0 Disable
1 Enable
bit 9 CT32B0 Enables clock for 32-bit counter/timer 0. reset value = 0
0 Disable
1 Enable
bit 10 CT32B1 Enables clock for 32-bit counter/timer 1. reset value = 0
0 Disable
1 Enable
So I will enable timer CT16B0 by setting bit 7 by the following statement.
LPC_SYSCON ->SYSAHBCLKCTRL |= (1 << 7); // Enable Clock for CT16B0
4. Setting PWM control
LPC11xx.h has the following struct definition and declaration for timers (and GPIO).
typedef struct
{
__IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */
__IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register */
__IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */
__IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */
__IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */
__IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */
__IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */
__IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */
__IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */
__IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */
__IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */
__I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */
uint32_t RESERVED1[3];
__IO uint32_t EMR; /*!< Offset: 0x03C (R/W) External Match Register */
uint32_t RESERVED2[12];
__IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */
__IO uint32_t PWMC; /*!< Offset: 0x074 (R/W) PWM Control Register */
} LPC_TMR_TypeDef;
/* Peripheral declaration */
...
#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
...
/* Peripheral memory map */
/* Base addresses */
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_AHB_BASE (0x50000000UL)
/* APB0 peripherals */
#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
/* AHB peripherals */
#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
/ to be continued, ...
************************************************************************************
18.7.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not cause an interrupt, but a Match register can be used to detect an overflow if needed.
Table 282. Timer Control Register (TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004)
0 CEn Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero,
the counters are disabled. 0
1 CRst Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next
positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 0
31:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not
18.7.3 Timer Counter (TMR16B0TC - address 0x4000 C008 and TMR16B1TC - address 0x4001 0008)
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
Table 283: Timer counter registers (TMR16B0TC, address 0x4000 C008 and TMR16B1TC
0x4001 0008)
15:0 TC Timer counter value. 0
31:16 - Reserved
18.7.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and TMR16B1PR - address 0x4001 000C)
The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.
Table 284: Prescale registers (TMR16B0PR, address 0x4000 C00C and TMR16B1PR
0x4001 000C)
15:0 PR Prescale max value.
18.7.5 Prescale Counter register (TMR16B0PC - address 0x4000 C010 and TMR16B1PC - address 0x4001 0010)
The 16-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Table 285: Prescale counter registers (TMR16B0PC, address 0x4001 C010 and TMR16B1PC
0x4000 0010)
15:0 PC Prescale counter value. 0
31:16 - Reserved.
18.7.6 Match Control Register (TMR16B0MCR and TMR16B1MCR)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in Table 286.
Table 286. Match Control Register (TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014)
0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0
1 Enabled
0 Disabled
1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 0
1 Enabled
0 Disabled
2 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
0
1 Enabled
0 Disabled
3 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0
1 Enabled
0 Disabled
4 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 0
1 Enabled
0 Disabled
5 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
0
1 Enabled
0 Disabled
6 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0
1 Enabled
0 Disabled
7 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 0
1 Enabled
0 Disabled
8 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
0
1 Enabled
0 Disabled
9 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0
1 Enabled
0 Disabled
10 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 0
1 Enabled
0 Disabled
11 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
0
1 Enabled
0 Disabled
31:12 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
18.7.7 Match Registers (TMR16B0MR0/1/2/3 - addresses 0x4000
C018/1C/20/24 and TMR16B1MR0/1/2/3 - addresses 0x4001 0018/1C/20/24)
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Table 287: Match registers (TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and
TMR16B1MR0 to 3, addresses 0x4001 0018 to 24)
15:0 MATCH Timer counter match value. 0
31:16 - Reserved.
18.7.8 Capture Control Register (TMR16B0CCR and TMR16B1CCR)
The Capture Control Register is used to control whether the Capture Register is loaded
with the value in the Counter/timer when the capture event occurs, and whether an
interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, n represents the Timer number, 0 or 1.
Table 288. Capture Control Register (TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address
0x4001 0028)
0 CAP0RE Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will
cause CR0 to be loaded with the contents of TC. 0
1 Enabled
0 Disabled
1 CAP0FE Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will
cause CR0 to be loaded with the contents of TC. 0
1 Enabled
0 Disabled
2 CAP0I Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will
generate an interrupt. 0
1 Enabled
0 Disabled
31:3 - - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
18.7.9 Capture Register (CT16B0CR0 - address 0x4000 C02C and CT16B1CR0 - address 0x4001 002C)
Each Capture register is associated with a device pin and may be loaded with the
counter/timer value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Table 289: Capture registers (TMR16B0CR0, address 0x4000 C02C and TMR16B1CR0,
address 0x4001 002C)
15:0 CAP Timer counter capture value. 0
31:16 - Reserved.
18.7.10 External Match Register (TMR16B0EMR and TMR16B1EMR)
The External Match Register provides both control and status of the external match
channels and external match pins CT16B0_MAT[2:0] and CT16B1_MAT[1:0].
If the match outputs are configured as PWM output in the PWMCON registers
(Section 18.7.12), the function of the external match registers is determined by the PWM
rules (Section 18.7.13 “Rules for single edge controlled PWM outputs” on page 336).
18.7.11 Count Control Register (TMR16B0CTCR and TMR16B1CTCR)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edges for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs, and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, duration of the HIGH/LOW levels on the same CAP input in
this case can not be shorter than 1/(2 PCLK).
Table 292. Count Control Register (TMR16B0CTCR - address 0x4000 C070 and
TMR16B1CTCR - address 0x4001 0070)
1:0 CTM Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or clear
PC and increment Timer Counter (TC). 00
0x0 Timer Mode: every rising PCLK edge
0x1 Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
0x2 Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
0x3 Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
3:2 CIS Count Input Select. In counter mode (when bits 1:0 in this
register are not 00), these bits select which CAP pin is
sampled for clocking. Note: If Counter mode is selected in
the CTCR register, bits 2:0 in the Capture Control Register
(CCR) must be programmed as 000. 00
0x0 CT16Bn_CAP0
0x1 CT16Bn_CAP1
0x2 Reserved.
0x3 Reserved.
31:4 - - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
18.7.12 PWM Control register (TMR16B0PWMC and TMR16B1PWMC)
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For timer 0, three single-edge controlled PWM outputs can be selected on the
CT16B0_MAT[2:0] outputs. For timer 1, two single-edged PWM outputs can be selected
on the CT16B1_Mat[1:0] outputs. One additional match register determines the PWM
cycle length. When a match occurs in any of the other match registers, the PWM output is
set to HIGH. The timer is reset by the match register that is configured to set the PWM
cycle length. When the timer is reset to zero, all currently HIGH match outputs configured
as PWM outputs are cleared.
Table 293. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and
TMR16B1PWMC- address 0x4001 0074)
0 PWMEN0 PWM channel0 enable 0
0 CT16Bn_MAT0 is controlled by EM0.
1 PWM mode is enabled for CT16Bn_MAT0.
1 PWMEN1 PWM channel1 enable 0
0 CT16Bn_MAT1 is controlled by EM1.
1 PWM mode is enabled for CT16Bn_MAT1.
2 PWMEN2 PWM channel2 enable 0
0 Match channel 2 or pin CT16B0_MAT2 is controlled by
EM2. Match channel 2 is not pinned out on timer 1.
1 PWM mode is enabled for match channel 2 or pin
CT16B0_MAT2.
3 PWMEN3 PWM channel3 enable
Note: It is recommended to use match channel 3 to set
the PWM cycle because it is not pinned out.
0
0 Match channel 3 match channel 3 is controlled by EM3.
1 PWM mode is enabled for match channel 3match
channel 3.
31:4 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
18.7.13 Rules for single edge controlled PWM outputs
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
(timer is set to zero) unless their match value is equal to zero.
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
3. If a match value larger than the PWM cycle length is written to the match register, and
the PWM signal is HIGH already, then the PWM signal will be cleared on the next start
of the next PWM cycle.
4. If a match register contains the same value as the timer reset value (the PWM cycle
length), then the PWM output will be reset to LOW on the next clock tick. Therefore,
the PWM output will always consist of a one clock tick wide positive pulse with a
period determined by the PWM cycle length (i.e. the timer reload value).
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
timer goes back to zero and will stay HIGH continuously.
Note: When the match outputs are selected to serve as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0
except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to 1 to enable the timer reset when the timer value matches the value of the
corresponding match register.
.END
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