SYSAHBCLKCTRL bit 16 (IOCON) problem - lpcware
PWM for LPC1114 - tombond Fri, 2012-03-16 08:12
http://www.lpcware.com/content/forum/pwm-for-lpc1114
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Hi,
I'm a student from germany and atm I'm doing a little project using the LPC1114/302. Therefore I need a 2730Hz 50% PWM.
Now what I did was:
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8); // Enable Clock for TMR1
LPC_IOCON->PIO1_9 |= (1<<0); // PIN1_9 = CT16B1_MAT0
LPC_TMR16B1->MR0 = 2200; // 50% Duty Cycle
LPC_TMR16B1->MR3 = 4400; // Cycle Length
LPC_TMR16B1->MCR |= (1<<10); // TC Reset on MR3 Match
LPC_TMR16B1->PWMC |= (1<<0); // PWM Mode
LPC_GPIO1->DIR |= (1<<9); // Output
LPC_TMR16B1->TCR |= (1<<0); // GO
but the Pin1_9 stays 3,3V without any changes.
Even LPC_TMR16B1->EMR &= ~(1<<0); didn't change a thing, it still is high.
Does anybody know what I'm doing wrong?
EDIT: While debugging, I just found out that writing the IOCON->PIO1_9 isn't working. Any ideas?
Thanks,
Thomas
Fri, 2012-03-16 08:46 #1 Ex-Zero
This part of your code is working
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8); // Enable Clock for TMR1
LPC_IOCON->PIO1_9 |= (1<<0); // PIN1_9 = CT16B1_MAT0
LPC_TMR16B1->MR0 = 2200; // 50% Duty Cycle
LPC_TMR16B1->MR3 = 4400; // Cycle Length
LPC_TMR16B1->MCR |= (1<<10); // TC Reset on MR3 Match
LPC_TMR16B1->PWMC |= (1<<0); // PWM Mode
LPC_TMR16B1->TCR |= (1<<0); // GO
and doing exactly what it should: generating 50% 10909 Hz PWM (at 48MHz).
If you don't see PIO1_9 changing, use your debugger to check all registers you've used. Probably you've changed some settings (SystemInit() ?) and now that's surprising you
Edit: If IOCON isn't working SYSAHBCLKCTRL bit 16 (IOCON) is reset :rolleyes:
Fri, 2012-03-16 09:05 #2 tombond
Thank you very very much!
Enabling the IOCON bit solved the problem, but still I don't get why
Do I have to set this bit to make changes in IOCON possible?
I never thought of this because in aaaall the threads around here no one ever said anything about enabling this bit xD
Could you please explain to me why I had to do this?
Thanks for your time,
Thomas
Fri, 2012-03-16 09:22 #3
Do I have to set this bit to make changes in IOCON possible?
Yes
Usually CMSIS is doing that for you (therefore that's not mentioned in samples) in system_LPC11xx.c:
#define AHBCLKCTRL_Val 0x0001005F
...
LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val;
If you don't use CMSIS or set AHBCLKCTRL yourself, default value is used and bit 16 is reset
Fri, 2012-03-16 09:37 #4 tombond
Thanks again for the explanation.
I'm not using CMSIS because I use IBM Rational Rhapsody to create a UML model, the Strauss bridge by Willert and µVision from Keil.
A professor here at my school gave me a short introduction to all this stuff but I have a really hard time getting into it.
I copied my system_lpc11xx.c from a Keil demo project called "RTX_Blinky", so I don't know if it's possible to use CMSIS with µVision instead of LPCXpresso.
.END
// ***********************************************************************
// Program - PWM Blinky
// Description - Blink Somy Board LED PIO0_8 using PWM
// Build - 2013.08.08.02
// Date - 2013aug09hkt1259
// Author - TL Fong (fongmcu.blogspot.hk, tlfong01hongkong@google.com)
// Hardware - NXP ARM Cortex M0 LPC1114FBD48/302
// IDE - MDK-Lite/uVision 4.71, CoLinkEx 1.1, Flash Magic v7.51
// References -
// 1. UM10398 LPC111x/LPC11Cxx User manual R12 2012sep24
// 2. LPC11xx.h CMSIS Cortex-M0 Core Peripheral Access Layer Header File
// for NXP LPC11xx/LPC11Cxx V1.10 2010nov24
// Notes -
// 1. PWM pin configuration
// PIO0_8/MISO0/CT16B0_MAT0 = Somy LPC1114 Eval Board P4 Pin 3
// ***********************************************************************
void testXiaBoardPwmBlinky03()
{
// Enable System AHB clock for CT16B0 timer (Table 21 bit 7 CT16B0)
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); // CT16B0 = 1 enables CT16B0
// Enable System AHB clock for IOCON block (Table 21 bit 16 IOCON)
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 16);
// Set function of PIO0_8 pin (UM10398 Table 79 bits 2:0 FUNC)
LPC_IOCON->PIO0_8 &= ~0x7; // FUNC = 0x2 selects function
LPC_IOCON->PIO0_8 |= 0x2; // CT16B0_MAT0
// Set PWM mode for CT16B0_MAT0,3 (Table 293 bit 0 PWMEN0, bit3 PWMEN3)
LPC_TMR16B0->PWMC |= 0x9; // PWMENO, PWMEN3 = 1 enables MR0, MR3
// Set External Match Register (Tables 290, 291)
LPC_TMR16B0->EMR = (0x3 | 0x1); // bits 4, 5 = 11 toggle, bit 0 = 1 ?
// Resets timer counter on a match (Table 286 bit 10 MR3R)
LPC_TMR16B0->MCR |= 0x400; // MR3R = 1 resets counter on MR3 match
// Set prescale 12000 count of AHB clock = 240 uS (Table 279 TMR16B0PR)
LPC_TMR16B0->PR = 12000; // (1/(50,000,000/2) x 12000 = 240 uS
// Set cycle length (Table 279 TMR16B0MR3, Figure 68)
LPC_TMR16B0->MR3 = 4000; // 240uS x 4000 = 0.96 == 1 second
// Set duty cycle (Table 279 TMR16B0MR0, Figure 68)
LPC_TMR16B0->MR0 = 2000; // 240uS x 2000 == 0.5 second (50% duty cycle)
// Start timer (Table 279 TMR16B0CTCR bit0 CEn)
LPC_TMR16B0->TCR |= 0x1; // CEn = 1 enables timer
while (1)
{
// loop forever
}
}
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