LPC1114 GPIO Ports simulation learning notes

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Peripheral Simulation For NXP (founded by Philips) LPC1114/301 — GPIO Ports 0-3 (42 bits)


Simulation support for this peripheral or feature is comprised of:
  • Dialog boxes which display and allow you to change peripheral configuration.
  • VTREGs (Virtual Target Registers) which support I/O with the peripheral.
These simulation capabilities are described below.

General Purpose I/O 0 Dialog

General Purpose I/O 0
The General Purpose Input/Output (GPIO) Dialog controls the direction of the general purpose port pins. You may use the following controls to select and configure the external interrupt settings.
GPIO Group
  • Mask (Input Output Mask Register) allows or inhibits the access (using SET or CLR) of each I/O port bit. The checkboxes are checked to inhibit port pin access and unchecked for allow port pin access.
  • GPIOnDATA (Input Output Set Register) bits are checked or unchecked to show or set each port bit.
  • GPIOnDIR (Input Output Direction Register) contains the direction assignments for each I/O port bit. The checkboxes are checked for output and unchecked for input.
  • GPIOnCLR (Input Output Clear Register) bits are checked to force a low level for a that port bit during output.
Interrupt Control
  • GPIOnIS (Interrupt Sense Register) configures the interrupt on a pin to be edge (unchecked) or level (checked) sensitive.
  • GPIOnIBE (Interrupt Both Edges Register) configures the interrupt to be triggered on both leading and trailing edges.
  • GPIOnIEV (Interrupt Event Register) configures the interrupt on a pin to be triggered rising or falling edges.
  • GPIOnIE (Interrupt Mask Register) masks the interrupt on a pin when unchecked.
  • GPIOnRIS (Raw Interrupt Status Register) checked when all interrupt requirements have been met prior to the trigger.
  • GPIOnMIS (Masked Interrupt Status Register) checked when an interrupt triggers.
  • GPIOnIC (Interrupt Clear Register) when checked clears the interrupt edge detection logic.
I/O Port
  • Pins is used to manually control a pin value.

General Purpose I/O 1 Dialog

General Purpose I/O 1
The General Purpose Input/Output (GPIO) Dialog controls the direction of the general purpose port pins. You may use the following controls to select and configure the external interrupt settings.
GPIO Group
  • Mask (Input Output Mask Register) allows or inhibits the access (using SET or CLR) of each I/O port bit. The checkboxes are checked to inhibit port pin access and unchecked for allow port pin access.
  • GPIOnDATA (Input Output Set Register) bits are checked or unchecked to show or set each port bit.
  • GPIOnDIR (Input Output Direction Register) contains the direction assignments for each I/O port bit. The checkboxes are checked for output and unchecked for input.
  • GPIOnCLR (Input Output Clear Register) bits are checked to force a low level for a that port bit during output.
Interrupt Control
  • GPIOnIS (Interrupt Sense Register) configures the interrupt on a pin to be edge (unchecked) or level (checked) sensitive.
  • GPIOnIBE (Interrupt Both Edges Register) configures the interrupt to be triggered on both leading and trailing edges.
  • GPIOnIEV (Interrupt Event Register) configures the interrupt on a pin to be triggered rising or falling edges.
  • GPIOnIE (Interrupt Mask Register) masks the interrupt on a pin when unchecked.
  • GPIOnRIS (Raw Interrupt Status Register) checked when all interrupt requirements have been met prior to the trigger.
  • GPIOnMIS (Masked Interrupt Status Register) checked when an interrupt triggers.
  • GPIOnIC (Interrupt Clear Register) when checked clears the interrupt edge detection logic.
I/O Port
  • Pins is used to manually control a pin value.

General Purpose I/O 2 Dialog

General Purpose I/O 2
The General Purpose Input/Output (GPIO) Dialog controls the direction of the general purpose port pins. You may use the following controls to select and configure the external interrupt settings.
GPIO Group
  • Mask (Input Output Mask Register) allows or inhibits the access (using SET or CLR) of each I/O port bit. The checkboxes are checked to inhibit port pin access and unchecked for allow port pin access.
  • GPIOnDATA (Input Output Set Register) bits are checked or unchecked to show or set each port bit.
  • GPIOnDIR (Input Output Direction Register) contains the direction assignments for each I/O port bit. The checkboxes are checked for output and unchecked for input.
  • GPIOnCLR (Input Output Clear Register) bits are checked to force a low level for a that port bit during output.
Interrupt Control
  • GPIOnIS (Interrupt Sense Register) configures the interrupt on a pin to be edge (unchecked) or level (checked) sensitive.
  • GPIOnIBE (Interrupt Both Edges Register) configures the interrupt to be triggered on both leading and trailing edges.
  • GPIOnIEV (Interrupt Event Register) configures the interrupt on a pin to be triggered rising or falling edges.
  • GPIOnIE (Interrupt Mask Register) masks the interrupt on a pin when unchecked.
  • GPIOnRIS (Raw Interrupt Status Register) checked when all interrupt requirements have been met prior to the trigger.
  • GPIOnMIS (Masked Interrupt Status Register) checked when an interrupt triggers.
  • GPIOnIC (Interrupt Clear Register) when checked clears the interrupt edge detection logic.
I/O Port
  • Pins is used to manually control a pin value.

General Purpose I/O 3 Dialog

General Purpose I/O 3
The General Purpose Input/Output (GPIO) Dialog controls the direction of the general purpose port pins. You may use the following controls to select and configure the external interrupt settings.
GPIO Group
  • Mask (Input Output Mask Register) allows or inhibits the access (using SET or CLR) of each I/O port bit. The checkboxes are checked to inhibit port pin access and unchecked for allow port pin access.
  • GPIOnDATA (Input Output Set Register) bits are checked or unchecked to show or set each port bit.
  • GPIOnDIR (Input Output Direction Register) contains the direction assignments for each I/O port bit. The checkboxes are checked for output and unchecked for input.
  • GPIOnCLR (Input Output Clear Register) bits are checked to force a low level for a that port bit during output.
Interrupt Control
  • GPIOnIS (Interrupt Sense Register) configures the interrupt on a pin to be edge (unchecked) or level (checked) sensitive.
  • GPIOnIBE (Interrupt Both Edges Register) configures the interrupt to be triggered on both leading and trailing edges.
  • GPIOnIEV (Interrupt Event Register) configures the interrupt on a pin to be triggered rising or falling edges.
  • GPIOnIE (Interrupt Mask Register) masks the interrupt on a pin when unchecked.
  • GPIOnRIS (Raw Interrupt Status Register) checked when all interrupt requirements have been met prior to the trigger.
  • GPIOnMIS (Masked Interrupt Status Register) checked when an interrupt triggers.
  • GPIOnIC (Interrupt Clear Register) when checked clears the interrupt edge detection logic.
I/O Port
  • Pins is used to manually control a pin value.

PORTx VTREG

Data Type: unsigned long

The PORTx VTREGs represent the I/O pins of the simulated MCU for Port A, Port B, and so on. PORTA represents Port A, PORTB represents Port B, etc. You may read PORTx to determine the state of the output pins of that port. For example, in the command window you may type,
PORTA
to obtain value corresponding to the set pins of Port A. You may also change the input values of port pins by changing the value of the VTREG. For example,
PORTA=0x000000F0
sets the upper four port pins of Port A to a value of 1 and all other port pins to a value of 0. You may use the bitwise operators AND(&), OR(|) and XOR(^) to change individual bits of the PORTx VTREGs. For example:
PORTA |=  0x00000001;  /* Set PA0 Pin */
PORTB &= ~0x00000200;  /* Clr PB9 Pin */
PORTA ^=  0x00800000;  /* Toggle PA23 Pin */


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