(LPC_GPIO_TypeDef *) LPC_GPIO0_BASE - What does it mean?

I read the C Preprocessor article by Wikipedia and understands the following.

1.  The seemingly useless brackets are actually useful to avoid misinterpretion.  The redundant brackets does no harm otherwise.  For example, the following numerical expressions are same in value.

2 + 3

((2) + (3)) 


2.  The strange name LPC_GPIO_TypeDef;

seems to be the name of typedef of a structure below.   

But I am still confused by the define of #define LPC_GPIOx.  Need to read and think harder. 



LPC11xx.h

...

/*------------- General Purpose Input/Output (GPIO) --------------------------*/

typedef struct
{
  union {
    __IO uint32_t MASKED_ACCESS[4096];  /*!< Offset: 0x0000 (R/W) Port data Register for pins PIOn_0 to PIOn_11 */
    struct {
         uint32_t RESERVED0[4095];
    __IO uint32_t DATA;                 /*!< Offset: 0x3FFC (R/W) Port data Register */
    };
  };
       uint32_t RESERVED1[4096];
  __IO uint32_t DIR;                    /*!< Offset: 0x8000 (R/W)  Data direction Register */
  __IO uint32_t IS;                     /*!< Offset: 0x8004 (R/W)  Interrupt sense Register */
  __IO uint32_t IBE;                    /*!< Offset: 0x8008 (R/W)  Interrupt both edges Register */
  __IO uint32_t IEV;                    /*!< Offset: 0x800C (R/W)  Interrupt event Register */
  __IO uint32_t IE;                     /*!< Offset: 0x8010 (R/W)  Interrupt mask Register */
  __I  uint32_t RIS;                    /*!< Offset: 0x8014 (R/ )  Raw interrupt status Register */
  __I  uint32_t MIS;                    /*!< Offset: 0x8018 (R/ )  Masked interrupt status Register */
  __O  uint32_t IC;                     /*!< Offset: 0x801C ( /W)  Interrupt clear Register */
} LPC_GPIO_TypeDef;

...

/******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/
/* Base addresses                                                             */
#define LPC_FLASH_BASE        (0x00000000UL)
#define LPC_RAM_BASE          (0x10000000UL)
#define LPC_APB0_BASE         (0x40000000UL)
#define LPC_AHB_BASE          (0x50000000UL)

/* APB0 peripherals                                                           */
...

/* AHB peripherals                                                            */
#define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)
#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)
#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)
#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x20000)
#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x30000)

/******************************************************************************/
/*                         Peripheral declaration                             */
/******************************************************************************/

...

#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )